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19-2708; Rev 0; 4/03
+48V, Single-Port Network Power Switch For Power-Over-LAN
General Description
The MAX5922A/B/C is a single-port network power controller with an integrated power MOSFET, operating from a +32V to +60V supply rail. The device is specifically designed for power-sourcing equipment (PSE) in powerover-LAN applications and is fully compliant to the IEEE 802.3af standard. The MAX5922 provides power devices (PD) discovery, classification, current limit, and other necessary functions for an IEEE 802.3af compliant PSE. The MAX5922 is suitable for PSE function in both switch/router systems where the power is delivered to the load through the signal pairs, and in midspan systems where the power is delivered to the load through the spare pairs. In midspan mode, a detection collision avoidance circuit (MAX5922A/C only) provides the necessary back-off timing to prevent fault detections that happen when two different PSEs try to detect and power the same PD. The MAX5922B/C have a detection disable input that can be connected high to disable the detection/classification functions or connected low to enable them. The MAX5922 features a programmable undervoltage lockout (UVLO) that keeps the device in shutdown until the input voltage exceeds a certain threshold, set to 38V (MAX5922A) or 28V (MAX5922B/C) internally. After successfully discovering and classifying a PD, the MAX5922 enters startup mode. During startup, the MAX5922 limits the output voltage and current slew rate to minimize EMI (electromagnetic interference). The MAX5922 has an integrated 0.45 N-channel power MOSFET that provides efficient operation and simplified system design. The MAX5922 monitors and provides current-limit protection to the load at all times. The current limit is programmable using an external current-sensing resistor. The MAX5922 features current-limit foldback and duty-cycle limit to ensure robust operation during load-fault and short-circuit conditions. Fault management allows the part to either latch-off or autorestart after a fault. The MAX5922 provides POK, ZC, and FAULT status signals to indicate output power is good, zero-current fault, and other faults (overcurrent, overtemperature), respectively. The MAX5922 is available in a 28-pin TSSOP package and is rated over the extended -40C to +85C temperature range. o IEEE 802.3af Compliant o +32V to +60V Wide Operating Input Range o 0.45 Integrated Power Switch o Power Device (PD) Detection and Classification o 100A PD Leakage Detection Tolerant o Programmable Current Limit o Zero-Current Detection with Status Output o Detection Collision Avoidance Option for Midspan Application o Input Logic Signals Compatible with 1.8V to 5V CMOS Logic o Separate Analog and Digital Grounds with Up to 4V Offset o Power-Good Status Output o Overcurrent and Overtemperature Protection with Status Outputs o Current-Limit Foldback with Timeout and DutyCycle Control o Latch or Autorestart Fault Management
Features
MAX5922
Ordering Information
PART MAX5922AEUI MAX5922BEUI MAX5922CEUI TEMP RANGE -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 28 TSSOP 28 TSSOP 28 TSSOP
Applications
Power-Sourcing Equipment (PSE) Power-Over-LAN/Power-Over-MDI (Media-Dependent Interface) Computer Telephony Single-Port Power Injector/Adapter Midspan Power Injector Switches/Routers with In-Line Power
Typical Application Circuits, Selector Guide, and Pin Configuration appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
+48V, Single-Port Network Power Switch For Power-Over-LAN MAX5922
ABSOLUTE MAXIMUM RATINGS
(All voltages with respect to AGND_S, unless otherwise noted.) IN ............................................................................-0.3V to +76V UVLO ........................................................................-0.3V to +6V VDIG to DGND ..........................................................-0.3V to +6V OUT .......................................................-0.3V to (VDRAIN + 0.3V) DRAIN ..........................................................-0.3V to (VIN + 0.3V) RDT.........................................................................-0.3V to +12V RCL to IN ................................................................-10V to +0.3V EN, DET_DIS, DCA, CLASS, ZC_EN, and LATCH to DGND ...........................................-0.3V to +6V POK, ZC, CL0, CL1, CL2, and FAULT to DGND......-0.3V to +6V DGND ..........................................................................-5V to +5V Maximum Current into Drain .................................................0.8A Maximum Current into POK, ZC, CL0, CL1, CL2, FAULT...20mA Continuous Power Dissipation (TA = +70C) 28-Pin TSSOP (Derate 12.8mW/C above +70C) .....1026mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = 48V, VDIG = 3.3V, AGND_S = AGND = DGND = 0V, RSENSE = 0.5 1%, UVLO = open, EN = VDIG, RRCL = 150 1%, RRDT = 18.2k 1%, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Analog Input Voltage Range Analog Input Supply Current Digital Input Voltage Range Digital Input Supply Current DGND to AGND Operating Voltage Range Current-Limit Response Time OUT Current-Limit Foldback Voltage Current-Limit Sense Voltage (VIN - VDRS) (Note 4) Current-Limit Sense Foldback Voltage (VIN - VDRS) Overcurrent Timeout DMOS On-Resistance Power-Off OUT Sink Current Maximum Output Voltage Slew Rate Maximum Output Current Slew Rate Power-OK Threshold (VIN - VOUT) POK Output Low Voltage POK Output Leakage Current dVOUT/dt dIOUT/dt VTHPOK VFBSTOP OUT shorted to AGND (Note 2) (Note 3) Maximum voltage across RSENSE at VOUT > VFBSTOP 0C to +70C VILIM_fb tOC RDSON VOUT = 0V OUT shorted to AGND (Note 5) IOUT = 100mA TA = +25C TA = +85C 198 203 64 50 SYMBOL VIN IIN VDIG IDIG VDIG = 5V -4 1 18 212 212 70 60 0.45 0.75 15 100 35 650 750 10 0.4 0.05 1 850 223 221 76 75 mV ms A V/ms A/ms mV % V A VIN = 60V, measured at AGND after OUT has stopped slewing 1.65 0.05 CONDITIONS MIN 32 1 TYP MAX 60 1.6 5.50 0.1 +4 UNITS V mA V mA V s V
VILIM
mV
EN = DGND, VOUT = 48V VOUT rising, no load VOUT rising, CLOAD = 100F VOUT rising, POK from low to high Hysteresis VPOK = 3.3V
VPOK_LOW IPOK = 3mA
2
_______________________________________________________________________________________
+48V, Single-Port Network Power Switch For Power-Over-LAN
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 48V, VDIG = 3.3V, AGND_S = AGND = DGND = 0V, RSENSE = 0.5 1%, UVLO = open, EN = VDIG, RRCL = 150 1%, RRDT = 18.2k 1%, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER POK Output Delay (Note 6) Zero-Current Detection Threshold Voltage (VIN - VDRS) ZC Output Low Voltage ZC Output Leakage Current Zero-Current Detection Delay Zero-Current Deglitch Time Thermal Shutdown Shutdown Autorestart Time UNDERVOLTAGE LOCKOUT MAX5922A UVLO floating, VIN rising Default VIN UVLO UVLOTH Hysteresis Referenced to AGND_S, VUVLO rising UVLO Comparator Threshold VREF Hysteresis UVLO Input Resistance LOGIC SIGNALS EN, LATCH, DCA, DET_DIS CLASS, and ZC_EN Input High Voltage EN, LATCH, DCA, DET_DIS CLASS, and ZC_EN Input Low Voltage EN, LATCH, DCA, DET_DIS CLASS, and ZC_EN Input Current EN Low Pulse Width FAULT, CL0, CL1 and CL2, Output Low Voltage FAULT, CL0, CL1 and CL2, Output Leakage Current VOL ISINK = 3mA VFAULT = VCL0 = VCL1 = VCL2 = 3.3V, CLASS = 0V 0.05 VIH 1.65V < VDIG < 5.5V 0.7 x VDIG 0.3 x VDIG 0.8 -1 3 0.4 1 +1 A s V A V MAX5922B/ MAX5922C MAX5922A MAX5922B/C MAX5922A MAX5922B/ MAX5922C MAX5922A MAX5922B/ MAX5922C 50 1.36 1.31 36 26 38 28 4.4 2.5 1.38 1.33 160 120 mV k 1.41 1.36 V 40 30 V tRESTART tZCDEL tZC_DEG SYMBOL tPOK_LOW CONDITIONS POK from high to low, VOUT falling MIN 1.0 74 2.7 TYP 1.4 88 3.75 MAX 1.8 102 4.8 0.4 0.05 300 350 10 150 30 1.60 1.92 2.24 1 400 UNITS ms mV V A ms ms C C s
MAX5922
tPOK_HIGH POK from low to high, VOUT rising VZCTH V ZC_LOW (Note 4) I ZC = 3mA V ZC = 3.3V ZC from high to low, IOUT falling (Note 7) IOUT rising Temperature rising Hysteresis LATCH = low (Note 8)
VIL
1.65V < VDIG < 2.0V 2.0V < VDIG < 5.5V
V
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3
+48V, Single-Port Network Power Switch For Power-Over-LAN MAX5922
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 48V, VDIG = 3.3V, AGND_S = AGND = DGND = 0V, RSENSE = 0.5 1%, UVLO = open, EN = VDIG, RRCL = 150 1%, RRDT = 18.2k 1%, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Detection Probe Voltage Phase I Detection Probe Voltage Phase II Detection Short-Circuit Current Valid PD Detected Lower-Limit Threshold Valid PD Detected Upper-Limit Threshold Total Detection Time Reject Capacitance During Detection Allowable Capacitance During Detection SYMBOL VPBI VPBII ISC_DET RPDL RPDH tdet CPDH CPDL RPD = 19k to 26.5k RPD = 19k to 26.5k 6 0.6 CONDITIONS RPD = 19k to 26.5k RPD = 19k to 26.5k OUT shorted to AGND (Note 9) (Note 9) MIN 3.6 7.2 0.68 15 26.5 170 TYP 4 8 MAX 4.4 8.8 1.50 19 33.0 196 UNITS V V mA k k ms F F
PD DETECTION (See Figure 3, PD Detection Section)
PD CLASSIFICATION (See PD Classification Mode Section) Classification Probe Voltage Classification Short-Circuit Current Classification Time Duration Total Detection and Classification Delay Time Class 0 to Class 1 Threshold Class 1 to Class 2 Threshold Class 2 to Class 3 Threshold Class 3 to Class 4 Threshold Default To Class 0 High-Current Lower-Limit Threshold Collision Detection Delay Time (MAX5922A/MAX5922C Only) VCLASS IOUT = 0.5mA to 45mA No load 48 15 21.3 191 5.5 13 21 31 43 DCA = high, RPD = 15k 2.38 6.5 14.5 23 33 46.5 2.8 3.22 15 20 28 65 26 230 7.5 16 25 35 V mA ms ms mA mA mA mA mA s
ISC_CLASS Shorted to AGND tCLASS tTOT ICLASS_1L ICLASS_1-2 ICLASS_2-3 ICLASS_3-4 ICLASS_4-0 tDCA From detection completion From channel-enabled to power delivered at the OUT pin
Note 1: All specifications are 100% production tested at TA = +25C, unless otherwise noted. All temperature limits are guaranteed by design. Note 2: This is the time from an output overcurrent or short-circuit condition until the output goes into regulated current limit. Note 3: OUT voltage above which the output current limit is at its full value (see Figure 8). Note 4: To be consistent with the IEEE 802.3af standard, choose RSENSE = 0.5 1%. Note 5: This is the time the part stays in current-limit mode during overload condition. After tOC elapses (or when the junction temperature hits +150C) the part shuts down. Note 6: See the Typical Operating Characteristics and Figure 6. Note 7: This is the delay from IOUT falling below the zero-current threshold until ZC goes low and the IC shuts down (see the Zero-Current Detection section). Note 8: See the Fault Management section. Note 9: PD is detected by the procedures specified by the IEEE 802.3af standard. A probe voltage VPBI (+4V typically) is forced at OUT and the current IS1 is measured after tDET/2. A second probe voltage VPBII (+8V typically) is then forced and IS2 measured after tDET / 2 again. The voltage increment is then divided by the difference of the two currents (IS2 - IS1). This is the PD resistance value. 4 _______________________________________________________________________________________
+48V, Single-Port Network Power Switch For Power-Over-LAN
Typical Operating Characteristics
(MAX5922A, VIN = 48V, VDIG, EN, LATCH, CLASS, and ZC_EN = 3.3V, DCA, AGND_S = AGND = DGND = 0V, RSENSE = 0.5 1%, UVLO floating, RRCL = 150k, RRDT = 18.2k, TA = +25C, unless otherwise noted.)
VIN SUPPLY CURRENT vs. INPUT VOLTAGE
MAX5922 toc01
MAX5922
VIN SUPPLY CURRENT vs. TEMPERATURE
MEASURED AT AGND
MAX5922 toc02
DIGITAL SUPPLY CURRENT vs. TEMPERATURE
11.9 11.8 11.7
MAX5922 toc03
1.00 MEASURED AT AGND 0.95 SUPPLY CURRENT (mA) 0.90 0.85 0.80 TA = -40C 0.75 0.70 32 37 42 47 52 57 TA = +25C TA = +85C
1.00 0.95 SUPPLY CURRENT (mA) 0.90 0.85 0.80 0.75 0.70 VIN = 48V VIN = 60V
12.0
IDIG (A)
11.6 11.5 11.4
VIN = 32V
11.3 11.2 11.1 11.0
62
-40 -25 -10
5
20
35
50
65
80
-40
-25
-10
5
20
35
50
65
80
INPUT VOLTAGE (V)
TEMPERATURE (C)
TEMPERATURE (C)
VIN UNDERVOLTAGE LOCKOUT vs. TEMPERATURE
MAX5922 toc04
MOSFET RDSON vs. TEMPERATURE
0.60 0.55 ON-RESISTANCE () 0.50 0.45 0.40 0.35 0.30 IOUT = 100mA
MAX5922 toc05
SENSE TRIP VOLTAGE vs. TEMPERATURE
214 SENSE TRIP VOLTAGE (V) 213 212 211 210 209 208 207 206 205 VIN = 32V VIN = 60V VIN = 48V
MAX5922 toc06
40.0 39.0 DEFAULT VIN UVLO (V) 38.0 37.0 36.0 35.0 34.0 33.0 32.0 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C) VIN FALLING VIN RISING
215
-40 -25 -10
5
20
35
50
65
80
-40 -25 -10
5
20
35
50
65
80
TEMPERATURE (C)
TEMPERATURE (C)
FOLDBACK-CURRENT LIMIT (ILIM vs. VOUT)
MAX5922 toc07
ZERO-CURRENT DETECTION THRESHOLD VOLTAGE vs. TEMPERATURE
MAX5922 toc08
ON-RESISTANCE vs. VDRAIN
IOUT = 100mA 0.7 ON-RESISTANCE () 0.6 TA = +25C 0.5 0.4 0.3 0.2 0.1 TA = -40C TA = +85C
MAX5922 toc09
ZERO-CURRENT THRESHOLD VOLTAGE (mV)
0.60 0.55 0.50 0.45 ILIM (A) 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0 5
3.70 3.68 3.66 3.64 3.62 3.60 3.58 3.56 3.54 3.52 3.50 -40 -25 -10 5 20 35 50 65 80 VIN = 32V VIN = 48V VIN = 60V
0.8
10 15 20 25 30 35 40 45 50 OUTPUT VOLTAGE (V)
28
32
36
40
44
48
52
56
60
TEMPERATURE (C)
INPUT VOLTAGE (V)
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5
+48V, Single-Port Network Power Switch For Power-Over-LAN MAX5922
Typical Operating Characteristics (continued)
(MAX5922A, VIN = 48V, VDIG, EN, LATCH, CLASS, and ZC_EN = 3.3V, DCA, AGND_S = AGND = DGND = 0V, RSENSE = 0.5 1%, UVLO floating, RRCL = 150k, RRDT = 18.2k, TA = +25C, unless otherwise noted.)
OVERCURRENT TIMEOUT (RLOAD FROM 240 TO 75)
MAX5922toc10
DIGITAL SUPPLY CURRENT vs. VDIG
30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 0 1.0 2.0 3.0 VDIG (V) 4.0 5.0
MAX5922 toc11
20V/div 0V 5V/div 0V 200mA/div 0A 5V/div 0V
VOUT
IDIG (A)
POK
IOUT
FAULT 20ms/div
6.0
SHORT-CIRCUIT RESPONSE TIME
MAX5922 toc12
POK LOW-TO-HIGH DELAY TIME
MAX5922 toc13
20V/div 0V 5V/div 0V 200mA/div 0A
VOUT
5V/div 0V
POK
POK 20V/div IOUT 0V VOUT
5V/div 0V 20ms/div
FAULT 100ms/div
POK HIGH-TO-LOW DELAY TIME
MAX5922 toc14
ZC TO OUT DELAY
MAX5922 toc15
20V/div 20V/div 0V VOUT 0V 5V/div 0V 5V/div 0V 1.25mA/div 0A
VOUT
POK ZC
5V/div 0V
POK
IOUT
1ms/div
400s/div
6
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+48V, Single-Port Network Power Switch For Power-Over-LAN
Typical Operating Characteristics (continued)
(MAX5922A, VIN = 48V, VDIG, EN, LATCH, CLASS, and ZC_EN = 3.3V, DCA, AGND_S = AGND = DGND = 0V, RSENSE = 0.5 1%, UVLO floating, RRCL = 150k, RRDT = 18.2k, TA = +25C, unless otherwise noted.)
ZERO-CURRENT HIGH-TO-LOW DETECTION TIME
MAX5922 toc16
MAX5922
ZERO-CURRENT (IIms GLITCH) DEGLITCH TIME
MAX5922 toc17
20V/div 0V 5V/div 0V 5V/div 0V 1.25mA/div 0A
VOUT
20V/div 0V
VOUT
POK ZC tZCDEL IOUT
5V/div 0V 5V/div 0V 200mA/div 0A
POK
GLITCH > tZC_DEG tZCDEL 100ms/div
ZC IOUT
100ms/div
ZERO-CURRENT DEGLITCH TIME (10ms GLITCH)
MAX5922 toc18
OVERCURRENT RESTART DELAY
MAX5922 toc19
20V/div 0V 5V/div 0V tZCDEL 5V/div 0V 200mA/div 0A 100ms/div GLITCH > tZC_DEG
VOUT
20V/div tRESTART 0V 5V/div 0V 500mA/div 0A 5V/div 0V 400ms/div
VOUT
POK
POK
ZC
IOUT
IOUT
FAULT
STARTUP WITH VALID PD (25k AND 0.1F)
MAX5922 toc20
STARTUP WITH INVALID PD (25k AND 10F)
MAX5922 toc21
20V/div 0V 5V/div 0V 5V/div 0V 200mA/div 0A 40ms/div
5V/div VOUT 0V 0V
VOUT POK
EN POK
250A/div 0A IOUT 2V/div 0V 100ms/div
IOUT
EN
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7
+48V, Single-Port Network Power Switch For Power-Over-LAN MAX5922
Typical Operating Characteristics (continued)
(MAX5922A, VIN = 48V, VDIG, EN, LATCH, CLASS, and ZC_EN = 3.3V, DCA, AGND_S = AGND = DGND = 0V, RSENSE = 0.5 1%, UVLO floating, RRCL = 150k, RRDT = 18.2k, TA = +25C, unless otherwise noted.)
STARTUP WITH INVALID PD (15k)
MAX5922 toc22
STARTUP WITH INVALID PD (33k)
MAX5922 toc23
5V/div 0V 0V
VOUT
5V/div 0V
VOUT
POK
0V
POK
250A/div 0A 2V/div 0V 100ms/div
250A/div 0A EN 2V/div 0V 40ms/div
IOUT
EN
STARTUP WITH OUTPUT SHORTED TO AGND
MAX5922 toc24
STARTUP WITH MIDSPAN MODE (DCA = VDIG, VALID PD (25k AND 0.1F))
MAX5922 toc25
5V/div 0V 5V/div 0V
20V/div VOUT POK 0V 5V/div 0V 5V/div 0V 500A/div 0A 100ms/div
VOUT
EN POK IOUT
500A/div 0A 2V/div 0V 100ms/div
IOUT
EN
STARTUP WITH MIDSPAN MODE (DCA = VDIG, INVALID PD (15k))
MAX5922 toc26
STARTUP WITH MIDSPAN MODE (DCA = VDIG, INVALID PD (33k))
MAX5922 toc27
5V/div 0V 0V
VOUT
5V/div 0V
VOUT
POK
0V
POK
250A/div 0A 2V/div 0V 400ms/div
IOUT
250A/div 0A IOUT EN 400ms/div
EN
2V/div 0V
8
_______________________________________________________________________________________
+48V, Single-Port Network Power Switch For Power-Over-LAN
Typical Operating Characteristics (continued)
(MAX5922A, VIN = 48V, VDIG, EN, LATCH, CLASS, and ZC_EN = 3.3V, DCA, AGND_S = AGND = DGND = 0V, RSENSE = 0.5 1%, UVLO floating, RRCL = 150k, RRDT = 18.2k, TA = +25C, unless otherwise noted.)
STARTUP WITH VALID PD (25k, ZC_EN = LOW)
MAX5922 toc28
MAX5922
STARTUP WITH DIFFERENT PD CLASSES
MAX5922 toc29
20V/div 0V
VOUT
VOUT
POK 0V 1.25mA/div 0A 5V/div 0V 100ms/div IOUT
0V 5V/div 0V 5V/div 0V
EN POK
SHORT TO AGND CLASS 4 CLASS 3 CLASS 2 CLASS 1 CLASS 0
IOUT
20mA/div EN 0A
40ms/div
OVERCURRENT TIMEOUT (RLOAD FROM 240 to 75)
MAX5922 toc30
OUTPUT SHORT-CIRCUIT RESPONSE
MAX5922 toc31
20V/div
VOUT 200mA/div IOUT
200mA/div
IOUT VOUT
5V/div
POK
20V/div
2ms/div
200s/div
OUTPUT SHORT-CIRCUIT RESPONSE
MAX5922 toc32
10A/div
IOUT
VOUT 20V/div
4s/div
_______________________________________________________________________________________
9
+48V, Single-Port Network Power Switch For Power-Over-LAN MAX5922
Pin Description
PIN * NAME AGND FUNCTION Analog Ground. This is the return of analog power input. AGND can vary 4V from DGND. AGND and DGND must be connected together at a single point in the system. Drain connection for the integrated MOSFET. Connect a sense resistor, RSENSE, from DRAIN to IN. These pins are also the current-sense resistor negative terminal. RSENSE sets the overcurrent-limit and open-circuit detection threshold. These two pins must be connected together. No Connection. Not internally connected. Leave pins 6 and 26 open. Pins 6 and 26 are left unconnected to provide additional spacing between the high-voltage pins and other pins. Input Voltage. Connect to a positive voltage source between +32V to +60V from IN to AGND. This is the current-sense resistor positive terminal. Bypass to AGND with a 47F, 100V electrolytic capacitor and a 0.1F, 100V ceramic capacitor. Place the ceramic capacitor close to this pin. Classification Sense Resistor. Connect a 150 1% resistor from RCL to IN for sensing the classification current. Leave RCL floating when the PD classification function is not used. Analog Ground Sense. Connect a 1 resistor from AGND_S to AGND. This resistor protects the IC during an output short-circuit condition. Undervoltage Lockout Adjustment Input. Referenced to AGND. Connect to the center point of a resistive-divider from IN to AGND to adjust the UVLO threshold. Leave open for default value. Detection Sense Resistor. Connect an 18.2k 1% resistor from RDT to AGND for sensing the PD detection current. Add a 680nF capacitor in parallel to this resistor to filter out the power-line noise. Connect RDT to AGND when the PD detection function is not used. Fault Signal Open-Drain Logic Output. Reference to DGND. FAULT is latched low when: 1. An overtemperature condition occurs and/or, 2. An overcurrent condition that has lasted for more than tOC. Power-OK, Open-Drain Logic Output. Reference to DGND. POK goes open drain a time tPOK_HIGH after VOUT raises to within VTHPOK from VIN. POK goes low a time tPOK_LOW after VOUT falls out of the VTHPOK from VIN. Zero-Current Fault Signal. Open-drain logic output. Reference to DGND. ZC is latched low when there is a zero-current condition lasting longer than tZCDEL. ZC is open-drain otherwise. The zero-current detection circuit is enabled immediately after the POK signal goes high. The ZC is unlatched after a valid PD has been detected and eventually classified. Must be Left Open or Connected to AGND Must be Left Open or Connected to AGND Must be Left Open or Connected to AGND Classification Report Logic Output Bit 2. See the PD Classification section (Table 2). Classification Report Logic Output Bit 1. See the PD Classification section (Table 2). Classification Report Logic Output Bit 0. See the PD Classification section (Table 2). Digital Ground. DGND can vary 4V from AGND. DGND and AGND must to be connected together at a single point in the system. Fault Management Selection Digital Input. Referenced to DGND. Connect to a logic high to latch off after a fault condition. Connect to a logic low for automatic restart after a fault condition (see the Fault Management section).
1, 2
DRAIN
3, 6, 26
N.C.
4
IN
5 7 8
RCL AGND_S UVLO
9
RDT
10
FAULT
11
POK
12
ZC
13 14 15 16 17 18 19
TP1 TP2 TP3 CL2 CL1 CL0 DGND
20
LATCH
*This is not a device pin. 10 ______________________________________________________________________________________
+48V, Single-Port Network Power Switch For Power-Over-LAN MAX5922
Pin Description (continued)
PIN 21 22 NAME ZC_EN EN FUNCTION Zero-Current-Detection Enable Logic Input. Referenced to DGND. Connect ZC_EN to a logic high to enable the zero-current detection circuitry. Connect ZC_EN to a logic low to disable this function. ON/OFF Control-Logic Input. Referenced to DGND. Connect to a logic high to enable the device. Connect to a logic low to disable the device and reset a latched-off condition. Digital Supply Voltage. VDIG is the supply voltage for the internal digital logic circuity. EN, LATCH, CLASS, DET_DIS, DCA, and ZC_EN input logic thresholds are automatically scaled to the voltage on VDIG. See the Typical Application Circuit for proper filtering. Classification Enable Digital Input. Connect to DGND to disable the classification function. Connect to VDIG to enable the classification function. PD Detection Disable Logic Input. When DET_DIS is connected to a logic high, the part skips the detection and classification (regardless of the status of CLASS) phases and powers on immediately after EN = high (MAX5922B/MAX5922C only). Detection Collision Avoidance Logic Input. Connect to a logic high to activate the detection collision avoidance circuitry for midspan system. Connect to DGND to disable this function. (MAX5922A only). See the Detection Collision Avoidance section. Output Voltage
23
VDIG
24
CLASS
DET_DIS 25 DCA 27, 28 OUT
VDIG FAULT N CHARGE PUMP
IN
CSP
ZC N ANALOG CONTROL POK N VOLTAGE REGULATOR N
DRAIN
OUT
UVLO
CLASS EN LATCH ZC_EN DCA LOGICLEVEL TRANSLATOR LOGIC CONTROL OSC
DETECTION AND CLASSIFICATION CIRCUITRY
RCL RDT
CL2 N CL1 N CL0
MAX5922
N DGND AGND
Figure 1. MAX5922 Block Diagram ______________________________________________________________________________________ 11
+48V, Single-Port Network Power Switch For Power-Over-LAN MAX5922
Detailed Description
The MAX5922 is a single-port network power controller with an integrated power MOSFET, operating from a +32V to +60V supply rail. The device is specifically designed for PSE in power-over-LAN applications and is fully compliant to the IEEE 802.3af standard. The MAX5922 provides PD discovery, classification, current limit, and other necessary functions for an IEEE 802.3afcompliant PSE. The MAX5922 operates in three different modes: PD detection mode, PD classification mode, and power mode. Figures 2 and 4 illustrates the device's functional operation.
Table 1. IEEE802.3af PD Specification
PARAMETER VALID PD DETECTION SIGNATURE 19k < RPD < 26.5k CPD < 0.6F Up to 2.0V Up to 12A NON-VALID PD DETECTION SIGNATURE 15k > RPD or RRD > 33k CPD > 6F -- --
V/I (Slope) Input Capacitance Offset Voltage Current Offset
PD Detection Mode
Once powered up and enabled, the MAX5922 probes the output for a valid PD. A valid PD should have a 25k discovery signature characteristic as specified in the IEEE 802.3af standard. Table 1 shows the IEEE 802.3af specification for a PSE detection of PDs (see the Typical Application Circuit and Figure 3 (MAX5922 startup sequence)). The MAX5922 performs the PD detection by forcing a probe voltage (VPBI = 4V) at the OUT pin and senses the current out of this pin. The sensed current is sampled and held tDET (88ms) after the probing voltage is sent. The probe voltage is then switched to VPBII = 8V. At the end of another tDET period, the ratio of the difference of the two test voltages and sensed currents (V/I) is calculated to determine the PD resistance. The MAX5922 PD detection circuitry checks for a valid PD resistive signature between 19k and 26.5k, with a parallel capacitance of up to 0.6F. The MAX5922 PD detection circuit rejects all PDs showing resistive signature of less than 15k or greater than 33k, and/or a capacitive signature greater than 6F. Any resistive signature between 15k to 19k, or between 26.5k to 33k, and/or a capacitance between 0.6F to 6F can produce unpredictable detection results. If the MAX5922 does not detect a valid PD signature, it continually sends the probe voltages to the output indefinitely (see Figure 5). The detection current reference is set by an external resistor (RRDT)) connected from the RDT pin to AGND. This resistor should be an 18.2k 1%, with an optional 680nF capacitor in parallel for filtering out power-line
noise. An internal diode in series with the detection voltage source and OUT is provided to restrict PD detection to the 1st quadrant as specified by the IEEE standard 802.3af (see Figure 3). To prevent damage to non-PD devices and to protect itself from output short circuit, the MAX5922 limits the current out of the OUT pin during PD detection to 1.5mA (max). For midspan systems where power is delivered to the PD through the spare pairs, the detection collision avoidance must be activated. In this mode, after every failed PD detection cycle, the MAX5922A/MAX5922C enter a back-off mode where they drive the OUT pin into high impedance for tDCA (2.8s). The DCA pin must be connected high (MAX5922A) to activate the detection collision avoidance circuitry (if connected low, the detection collision avoidance circuitry is disabled). The MAX5922C has the detection collision avoidance circuitry permanently enabled (see the Typical Application Circuit). After tDCA, the MAX5922A (with DCA high) and the MAX5922C resume PD detection operation. The MAX5922B has the detection collision avoidance circuitry permanently disabled.
Detection Enable/Disable
The MAX5922A has the PD detection mode permanently enabled. The MAX5922B/MAX5922C are equipped with a DET_DIS pin, which provides the option of enabling or disabling the power-device detection phase. With the DET_DIS pin connected high, the PD detection and classification phases are disabled regardless of the status of the class pin. With the DET_DIS pin connected low, the PD detection is enabled.
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+48V, Single-Port Network Power Switch For Power-Over-LAN MAX5922
N Y POWER-ON RESET VIN > UVLOTH? EN = HIGH? Y N RESET COUNTERS START PD DECTECTION FORCE OUT = VPBI (4V) WAIT I/2tDET Cl0 = CL1 = CL2 = HIGH SAMPLE AND HOLD ISENSE1
N FORCE VOUT = VCLASS (17.5V) WAIT tCLASS and MEASURE ICLASS
FORCE OUT = VPBI (8V) WAIT 1/2tDET
EN = LOW?
Y Y N LATCH = HIBH tRESTART ELAPSED? Y Y REPORT CLASS STATUS N N N START POWER-UP RESET FAULT AND ZC
START PD CLASSIFICATION CL0 = CL1 = CL2 = HIGH Y Y CLASS = H?
MEASURE IDET = ISENSE2 - ISENSE1
IS (VPBI - VPBI)/IDET OK? N Note 1 N IS DCA HIGH? Y WAIT tDCA OUTPUT IN HIGH-Z
SWITCH SHUTOFF FAULT = LOW
Y
THERMAL SHUTDOWN DETECTED?
OVERCURRENT DETECTED SWITCH SHUT-OFF ZC = LOW RESET tZCDEL Y Y N tZCDEL = 350ms? N VOUT - VIN < VTHPOK? POK LOW AFTER tPOK_DLY HIGH TO LOW RESET OVERCURRENT COUNTER N N OVERCURRENT CONDITION? N Y POK HIGH AFTER tPOK_DLY LOW TO HIGH N N Is IOUT < IZCTH? ZC_EN = HIGH? Y INCREMENT OVERCURRENT COUNTER OVERCURRENT COUNTER = 60?
INCREMENT tZCDEL
Y
Y
Y INCREMENT tZC_DEG RESET tZC_DEG N Y tZC_DEG = 10ms? RESET tZC_DEG tZCDEL
Y IS POK HIGH?
N
*FOR THE MAX5922B, THE DCA FUNCTION IS INTERNALLY DISABLED. FOR THE MAX5922C, THE DCA FUNCTION IS INTERNALLY ENABLED.
Figure 2. Operational Flow Chart (MAX5922A and MAX5922B/MAX5922C with DET_DIS Connected Low) ______________________________________________________________________________________ 13
+48V, Single-Port Network Power Switch For Power-Over-LAN MAX5922
POWER DEVICE INTERNAL TO MAX5922 27, 28 IMAX = 1.5mA VPROBE_VOLTAGE 7 AGND_S D1 RPD OUT
Figure 3. PSE Detection Source
N Y POWER-ON RESET VIN > UVLOTH?
N
EN = HIGH?
Y
START POWER-UP RESET FAULT, ZC
N
EN = LOW? Y Y N LATCH = HIGH? Y N
tRESTART ELAPSED
N SWITCH SHUT-OFF FAULT = LOW Y
N
Y
THERMAL SHUTDOWN DETECTED?
EN LOW TO HIGH TRANSACTION DETECTED?
OVERCURRENT DETECTED
SWITCH SHUT-OFF ZC = LOW RESET tZCDEL Y
Y
N tZCDEL = 350ms? N VOUT - VIN < VTHPOK? POK LOW AFTER tPOK_DLY HIGH TO LOW
RESET OVERCURRENT COUNTER
N OVERCURRENT = HIGH N Y Y INCREMENT OVERCURRENT COUNTER OVERCURRENT COUNTER = 60?
Y INCREMENT tZCDEL RESET tZC_DEG Y N
POK HIGH AFTER tPOK_DLY LOW TO HIGH N ZC_EN = HIGH?
IS IOUT < IZCTH? Y Y N IS POK HIGH? N Y tZC_DEG = 10ms? RESET tZC_DEG tZCDEL
INCREMENT tZC_DEG
Figure 4. Operational Flow Chart (MAX5922B/MAX5922C with DET_DIS Connected High) 14 ______________________________________________________________________________________
+48V, Single-Port Network Power Switch For Power-Over-LAN MAX5922
UVLO
VIN
8V VOUT
4V
0V tDET1 = 88ms tDET2 = 88ms
t
Figure 5. PD Detection with an Invalid PD Signature
Table 2. PD Classification Threshold Limits
SENSED CURRENT (mA) 0.5 to 4 or above 43 9 to 12 17 to 20 26 to 30 36 to 42 N/A N/A Power device not detected yet or CLASS pin connected low. CL2 0 0 0 0 1 1 1 1 CL1 0 0 1 1 0 0 1 1 CL0 0 1 0 1 0 1 0 1 Class 0 Class 1 Class 2 Class 3 Class 4 Not used Successful detection (classification disabled or DET_DIS = low) Detection ongoing CLASS TYPES
PD Classification Mode (PD Classification)
Following a valid PD detection, and if the CLASS pin is high, the MAX5922 enters the PD classification mode. If the CLASS pin is low, the PD classification mode is skipped and the MAX5922 goes directly from PD detection to the power mode. During the PD classification mode, the MAX5922 forces a probe voltage (17.5V) at the OUT pin and measures the current out of this pin. The measured current determines the class of the PD. The classification results are reported at the classification logic outputs CL0, CL1, CL2. Table 2 shows the classification threshold limits and the corresponding logic outputs CL0, CL1, and CL2.
Connect an external 150 1% resistor (RRCL) from RCL to IN to set the classification current reference. If the PD classification function is not used, RCL can be left floating. For the MAX5922B/MAX5922C, the DET_DIS pin must be connected low to enable the classification phase. If DET_DIS is connected high, the classification phase is disabled regardless of the state of the CLASS pin. After the classification phase, the MAX5922 enters power-up.
Power-Up Mode
After the PD is successfully detected and classified, the MAX5922 enters power-up mode. During this mode, the MAX5922 gradually turns on the integrated N-channel MOSFET. To minimize EMI, the MAX5922 limits the
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+48V, Single-Port Network Power Switch For Power-Over-LAN MAX5922
+48V 100V/ms (max)
+17.5V
+8V
VIN CROSSES UVLO
+4V
0V
POK (OPEN-DRAIN)
0V 0 tDET1, 88ms tDET2, 88ms tCLASS, 21.3ms tPOK_HIGH, 88ms
t
Figure 6. Startup Sequence
output voltage slew rate at the OUT pin to dVOUT/dt = 100V/ms (max) and the output-current slew rate out of the OUT pin to dIOUT/dt = 35A/ms (max). The MAX5922 has an integrated 0.45 N-channel power MOSFET. The MOSFET's drain is connected to the DRAIN pin and its source is connected to the OUT pin. The MAX5922 monitors and provides current-limit protection to the load at all times. The current limit is programmable using an external current-sensing resistor connected from IN to DRAIN. To be compatible with the IEE802.3af standard, use a 0.5 1%, 50ppm/C resistor. The MAX5922 features current-limit foldback and duty-cycle limit to ensure robust operation during load-fault and short-circuit conditions (see the Overcurrent Protection section). When V OUT is within 750mV of V IN for more than tPOK_HIGH, POK goes open drain. Figure 6 shows a typical startup sequence. After POK is asserted, the MAX5922 activates the zerocurrent detection function. This function monitors the output for an undercurrent condition and eventually turns off the power to the output if the PD is disconnected (see the Zero-Current Detection section).
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Undervoltage Lockout (UVLO)
The MAX5922 operates from a +32V to +60V supply voltage range and has a default UVLO set at +38V (MAX5922A) or +28V (MAX5922B/MAX5922C). The UVLO threshold is adjustable using a resistive-divider connected to the UVLO pin (see Figure 7). When the input voltage is below the UVLO threshold, all operation stops and the MOSFET is held off. When the input voltage is above the UVLO threshold and EN is high, the MAX5922 goes into operation. See Figures 2 and 4 for the operational flow charts. To adjust the UVLO threshold, connect an external resistive-divider from IN to UVLO and then from UVLO to AGND. Use the following equation to calculate the new UVLO threshold: R1 VUVLO _ TH = VREF 1 + R2 VREF is typically 1.38V (MAX5922A) or 1.33V (MAX5922B/ MAX5922C). The UVLO pin input resistance is 50k (min), keep the R1 and R2 parallel combination value at least 20 times smaller than 50k to minimize the new UVLO threshold error.
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+48V, Single-Port Network Power Switch For Power-Over-LAN
VIN = 32V TO 60V
IN R1
MAX5922
UVLO R2
AGND_S
Constant Current Limit The MAX5922 monitors V SENSE at all times during power mode and regulates the current through the power MOSFET as necessary to keep VSENSE (max) to the current-limit sense voltage (VILIM = 212mV). The load-current limit, ILIM, is programmed by the currentsense resistor, RSENSE, connected from IN to DRAIN (ILIM = VILIM/RSENSE). When the load current is less than ILIM, the MOSFET is fully on. When the load is trying to draw more than ILIM, the OUT pin works like a constant current source, limiting the output current to ILIM. If IOUT is at ILIM for greater than the current-limit timeout, a current-limit fault is generated and the power MOSFET is turned off (see the Overcurrent Timeout and Fault Management sections). Current Foldback While in current-limit condition, the voltage at the OUT pin drops. As the load resistance reduces (more loading), the output voltage reduces accordingly to maintain a constant load current. The power dissipation in the power MOSFET is (VDRAIN - VOUT) x ILIM. As the output voltage drops lower, more power is dissipated across the power MOSFET. To reduce this power dissipation, the MAX5922 offers a current foldback feature where it linearly reduces the VILIM value when VOUT drops below the OUT current-limit foldback voltage (VFBSTOP = 18V). Figure 8 illustrates this current foldback limit behavior. Overcurrent Timeout The MAX5922 keeps track of the time it is in current limit. An internal digital counter begins incrementing its count at 1count/ms when VSENSE exceeds its limit (either VILIM or VILIM foldback in foldback mode). The counter is reset to zero if the current falls back below the current limit. When the cumulative count reaches 60, an overcurrent fault is generated. After an overcurrent fault condition, the switch is turned off and the FAULT signal goes low (see Figure 9).
MAX5922
Figure 7. Setting Undervoltage Lockout with an External Resistive-Divider
Digital Logic
VDIG is the input supply for the internal logic circuitry. The logic input thresholds of EN, LATCH, CLASS, DCA (MAX5922A), DET_DIS (MAX5922B/MAX5922C), and ZC_EN are CMOS compatible and are determined by the voltage at V DIG which can range from 1.65V to 5.5V. The POK, ZC, CL0, CL1, CL2, and FAULT outputs are open drain. VDIG and all logic inputs and outputs are referenced to DGND. DGND is not connected to AGND internally and must be connected externally at a single point in the system to AGND. The maximum allowable difference in the voltage between DGND and AGND is 4V.
Enable (EN)
EN is a logic input to enable the MAX5922. Bringing EN low halts all operations and turns off the internal power MOSFET. When EN is high and the input voltage is above the UVLO threshold, the MAX5922 begins operating. Enable is also used to unlatch the part after a latched fault condition. This is done by toggling EN low and high again after a fault condition.
Overcurrent Protection
The MAX5922 provides a sophisticated overcurrent protection circuitry to ensure the device's robustness under output-current transient and current fault conditions. The current protection circuitry employs a constant current limit, a current foldback, and an overcurrent timeout. The device monitors the voltage drop, VSENSE (VSENSE = VIN - VDRAIN) to determine the load current.
VILM
VILM/3
VFBSTART (2V)
VFBSTOP (18V)
VOUT (V)
Figure 8. Current Foldback Characteristic ______________________________________________________________________________________ 17
+48V, Single-Port Network Power Switch For Power-Over-LAN MAX5922
This overcurrent timeout enables the MAX5922 to operate in a periodic overcurrent condition without causing a fault (see Figure 9).
Thermal Shutdown
If the MAX5922 die temperature reaches +150C, an overtemperature fault is generated. The MOSFET turns off and FAULT goes low. The MAX5922 die temperature must cool down below 120C before the overtemperature fault condition is removed (see Fault Management section).
Power-OK (POK)
POK goes open-drain tPOK_HIGH (88ms) after VOUT rises to within VTHPOK (0.75V) from VIN. POK goes low tPOK_LOW (1.4ms) after VOUT drops 0.82V below VIN.
Zero-Current Detection
Zero-current detection is enabled if ZC_EN is high and only after the startup period has finished (indicated by POK going high). When VSENSE falls below the zerocurrent threshold (VZCTH) for a continuous tZCDEL = 350ms, a zero-current fault is generated. The MOSFET is turned off and ZC is latched low. The MAX5922A and the MAX5922B/MAX5922C (with DET_DIS = low) immediately begin a PD detection sequence, regardless of the status of the LATCH input. ZC is unlatched and goes high impedance after a PD is detected. ZC is also high impedance during initial power-up. When DET_DIS is high (MAX5922B/MAX5922C), a zero-current fault shuts down the MOSFET and the EN pin needs to be toggled to unlatch the fault. At any time during a zero-current condition, if VSENSE goes above VZCTH for the zero-current deglitch time (tZC_DEG = 10ms), the zero-current counter resets to zero and a zero-current fault is not generated. Bring ZC_EN low to disable the zero-current detection function. ZC stays high impedance in this mode.
Fault Report (FAULT)
FAULT goes low when there is an overcurrent fault and/or an overtemperature fault. FAULT is open-drain otherwise. After a fault, the FAULT signal is latched low. FAULT is unlatched at the beginning of the next power mode.
Fault Management
The MAX5922 offers either latched-off or auto-retry fault management configurable by the LATCH input. Bringing LATCH high puts the device into latch mode while pulling LATCH low selects the autoretry option. In latch mode, the MAX5922 turns the MOSFET off and keeps it off after an overcurrent fault or an over-temperature fault. After the fault condition goes away, recycle the power supplies or toggle the EN pin low and high again to unlatch the part. However, the part waits a tRESTART period (1.92s) before recovering from a fault condition and resuming normal operation. In autoretry mode, the MAX5922 turns the MOSFET off after an overcurrent or overtemperature fault. After the fault condition is removed, the device waits a tRESTART period (1.92s) and then automatically restarts and enters the PD detection mode (MAX5922A and MAX5922B/MAX5922C with DET_DIS low). If DET_DIS is high (MAX5922B/MAX5922C), the MAX5922B/ MAX5922C automatically restart into the power-up mode after t RESTDRT . If the fault was due to an overtemperature condition, the MAX5922 waits for its die temperature to cool down below the hysteresis level before starting the tRESTART time.
ILIMIT
IOUT 0V
Detection Collision Avoidance
Detection collision avoidance is enabled by connecting the DCA pin directly to VDIG and disabled by connecting it to DGND. When DCA is high, the MAX5922A activates a back-off time, tDCA (2.8s), after every failed detection during PD detection mode. During this backoff time, the MAX5922A turns off the MOSFET and drives the OUT pin to high impedance. This function is required by the IEEE 802.3af standard if the PSE resides in a midspan system. After t DCA , the MAX5922A starts a PD detection sequence. The MAX5922B has this function internally disabled and the MAX5922C has this function internally enabled.
VFAULT 0V t tOC tRESTART t < tOC
Figure 9. Overcurrent Response 18 ______________________________________________________________________________________
+48V, Single-Port Network Power Switch For Power-Over-LAN
Selector Guide
PART MAX5922AEUI MAX5922BEUI MAX5922CEUI PIN-PACKAGE 28 TSSOP 28 TSSOP 28 TSSOP DETECTION COLLISION AVOIDANCE Selectable Disabled Enabled PD DETECTION DISABLE -- Selectable Selectable
MAX5922
Pin Configuration
TOP VIEW
DRAIN 1 DRAIN 2 N.C. 3 IN 4 RCL 5 N.C. 6 AGND_S 7 UVLO 8 RDT 9 FAULT 10 POK 11 ZC 12 TP1 13 TP2 14 28 OUT 27 OUT 26 N.C. 25 DET_DIS (DCA) 24 CLASS
Chip Information
TRANSISTOR COUNT: 8687 PROCESS: BiCMOS
MAX5922A MAX5922B MAX5922C
23 VDIG 22 EN 21 ZC_EN 20 LATCH 19 DGND 18 CL0 17 CL1 16 CL2 15 TP3
TSSOP
( ) MAX5922A ONLY.
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+48V, Single-Port Network Power Switch For Power-Over-LAN MAX5922
Typical Application Circuits
+48V POWER OVER SIGNAL PAIRS LAN SWITCH +48V IN RJ45 +48V OUT RJ45 PD CAT5 DATA POWER SENT OVER SIGNAL PAIRS POWERED DEVICE (IP PHONES, WIRELESS LAN ACCESS NODE, SECURITY CAMERA, ETC.) +48V POWER OVER SPARE PAIRS RJ45 RJ45 CAT5 MIDSPAN HUB +48V IN RJ45 +48V OUT RJ45 PD CAT5 POWERED DEVICE (IP PHONES, WIRELESS LAN ACCESS NODE, SECURITY CAMERA, ETC.)
MAX5922A/MAX5922B
MAX5922A/MAX5922C
POWER SENT OVER SPARE PAIRS
+48V 47F 100V RRCL 150 1% 0.1F 100V 8 5 9 RRDT 18.2k 1% 680nF 4 IN UVLO RCL RDT
RSENSE 0.5 1% 1, 2 DRAIN 27, 28 OUT VDIG POK FAULT ZC 11 10 12 24 20 21 22 25 19
48V OUTPUT TO PORT B1100LB 100V, 1A 100 10F 10V OPEN-DRAIN OUTPUTS REFERENCED TO DGND 1F 10V VDIG 1.65V TO 5.5V (REF TO DGND)
MAX5922
CLASS 18 CL0 CL1 CL2 LATCH ZC_EN EN DCA* 7 AGND_S DGND
OPEN-DRAIN OUTPUTS REFERENCED TO DGND 1 5% 1/16W
17 16
ON OFF CONNECT DCA TO VDIG FOR MIDSPAN MODE
AGND
NOTE: ALL SIGNAL AND DIGITAL INPUTS/OUTPUTS ARE REFERENCED TO DGND. DGND CAN BE 4V FROM AGND_S. *MAX5922A ONLY. MAX5922B/MAX5922C DO NOT HAVE A DCA PIN.
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+48V, Single-Port Network Power Switch For Power-Over-LAN
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
TSSOP4.40mm.EPS
MAX5922
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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